1. Field of the Invention
The present invention relates to a data processor, and to be further detailed, relates to a data processor realizing a high processing ability by means of a sophisticated pipeline processing mechanism.
2. Description of the Prior Art
With the development of the length of bits whereby processing of the data processor is performed from four bits, via 8 bits and 16 bits, to 32 bits, the method of designating the addressing mode, that is, the method of computing the execution address from the address designating part of an instruction has been diversified.
For example, disclosure is made on a data processing system for processing an instruction having a general-purpose addressing mode in the U.S. Pat. No. 4,241,397. An instruction processed by the central processing unit of this data processing system has a system as shown in FIG. 1.
Each instruction comprises an operation code 80 and operand specifiers 81, 82 and 83 which are information of designating addresses, and each operand specifiers comprises at least one data byte. FIG. 1 shows an example of an operand having three operand specifiers.
Each operand specifier consists of two fields. The high-order bits thereof which configurate a register mode field 84 can designate address modes from 0 to 15 as shown in FIG. 1, and the low-order bits thereof which configurate a register address field 85, can designate general-purpose registers. When an index address mode is specified like 84A for the register mode field of the operand specifier 83, one of the general-purpose registers to be used as an index register in processing the operand specifier is specified for the register field 85A corresponding to that mode. A secondary operand specifier is included in an instruction of index address operation.
This secondary operand specifier gives the base address whereto the content of the designated index register.
Thus, address calculation of this central processing unit takes-in the content of the index register designated by the first byte of the operand specifier, generates an address based on information which is comprised in the second byte and the following bytes of the operand specifier, compounds it with the content of the index register designated by the first byte, and thereby generates an address of an operand.
FIG. 2 is a diagram showing a pipeline configuration of a conventional data processor.
First, prefetching of an instruction is performed by an instruction prefetch circuit 86. Subsequently, the prefetched instruction is sequentially decoded by an instruction buffer decoding circuit 87. Then, an address of an operand is calculated by address calculation and an operand fetching circuit 88 and fetching of the operand is performed, and operation of the instruction is executed by an operation execution circuit 89.
When the index address mode is designated in the conventional data processor as mentioned above, firstly information relating to the index of the operand specifier is decoded by the instruction buffer decoding circuit 87, subsequently decoding of information comprised in the second byte and the following bytes of the operand specifier is completed, thereafter the actual address calculation is performed by the address calculation and the operand fetch circuit 88, and execution of operation is performed by the operation execution circuit 89. This means that the index value is precedingly decode-processed, and therefore information relating to the base value is obtained after that, and the address calculation can not be made while performing decoding processing.